Research Article: High Performance Amplifier Element Realization via MoS2/GaTe Heterostructures

Date Published: January 15, 2018

Publisher: John Wiley and Sons Inc.

Author(s): Xiao Yan, David Wei Zhang, Chunsen Liu, Wenzhong Bao, Shuiyuan Wang, Shijin Ding, Gengfeng Zheng, Peng Zhou.

http://doi.org/10.1002/advs.201700830

Abstract

2D layered materials (2DLMs), together with their heterostructures, have been attracting tremendous research interest in recent years because of their unique physical and electrical properties. A variety of circuit elements have been made using mechanically exfoliated 2DLMs recently, including hard drives, detectors, sensors, and complementary metal oxide semiconductor field‐effect transistors. However, 2DLM‐based amplifier circuit elements are rarely studied. Here, the integration of 2DLMs with 3D bulk materials to fabricate vertical junction transistors with current amplification based on a MoS2/GaTe heterostructure is reported. Vertical junction transistors exhibit the typical current amplification characteristics of conventional bulk bipolar junction transistors while having good current transmission coefficients (α ∼ 0.95) and current gain coefficient (β ∼ 7) at room temperature. The devices provide new attractive prospects in the investigation of 2DLM‐based integrated circuits based on amplifier circuits.

Partial Text

Device Fabrication and Electrical Characterization: This vertical HBT started with a commercially available Si‐wafer, slightly p‐doped with phosphorus. Before transferring MoS2, native oxide on the exposed Si substrate was carefully removed via the additional wet etching. Then, a few layers of MoS2 were exfoliated from the commercially available crystals on p‐type silicon substrates. After placing the MoS2 on the substrate, the wafer was annealed under vacuum (10−1 Pa) at 300 °C for 30 min, to remove any residue tapes. The insulating layer used for isolating the emitter and metal electrode from the collector was patterned using e‐beam lithography. Subsequently, without removing the photoresist, ≈40 nm of Al2O3 was deposited using the atomic layer deposition. Next, the photoresist was removed using acetone, after which only Al2O3 remained in the trenches and was washed away (with the resist) from the other regions. With the help of optical microscopy, the exfoliated GaTe was transferred directionally to the target MoS2 flake. Finally, electrode patterns were defined by a standard electron beam lithography (EBL) process and 10/60 nm Cr/Au electrodes were deposited via physical vapor deposition. Electrical properties of the fabricated devices were measured in a probe station using a semiconductor device parameter analyzer (Agilent, B1500A).

The authors declare no conflict of interest.

 

Source:

http://doi.org/10.1002/advs.201700830

 

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